

Tzi-cker Chiueh
Rank/Position Title:
Professor |
Home Page:
http://www.cs.sunysb.edu/~chiueh |
Date of original appointment to this faculty, followed by dates and ranks of advancement:
- January 1993, Assistant Professor
- January 1999, Associate Professor
- January 2004, Full Professor
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Degrees:
Degree |
Field |
Institution |
Date |
Ph.D. |
Computer Science |
University of California |
1992 |
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Conferences, workshops, and professional development:
- Computer architecture education workshop
- ACM Supercomputing conferences
- IEEE High-Performance Computer Architecture (HPCA) conference
- IEEE Supercomputing conference.
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Other related computing experience:
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Department, college, and/or university committee membership:
- Departmental graduate admission committee
- Departmental faculty recruiting committee
- Departmental computer operation committee
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Principal publications of the last five years:
- Li, C.; Peng, G.; Gopalan, K.; Chiueh, T., ``Performance Guarantee for Cluster-Based Internet Services'', Proceedings of IEEE CGrid 2003, p. 276-283, May 2003, Tokyo Japan.
- Gopalan, K.; Chiueh, T. ``Improving Route Lookup Performance Using Network Processor Cache,'' in Proceedings of IEEE Supercomputing 2002, p. 1-10, Baltimore, PA., November 2002.
- Mitra, T.; Chiueh, T., ``An FPGA Implementation of Triangle Mesh Decompression", 2002 IEEE Symposium on Field-Programmable Custom Computing Machines, April 2002.
- Mitra, T.; Chiueh, T., ``Compression Domain Parallel Mesh Rendering,'' Proceedings of International Parallel and Distributed Processing Symposium (ISDPS), Fort Launderdale, Florida, April 2002.
- Chiueh, T.; Mitra, T., ``Reusing BIST Logic for Intelligent DRAM,'' in a special issue of IEEE Technical Committee on computer Architecture Newsletter on the WIP session of HPCA-6, March 2000.
- Chiueh, T.; Pradhan, P., ``Cache Memory Design for Network Processors,'' in Proceedings of 6th International Symposium on High-Performance Computer Architecture, p. 409-416, Toulouse, France, January 2000.
- Mitra, T.; Chiueh, T., ``Dynamic 3D Graphics Workload Characterization and the Architectural Implications,'' in Proceedings of 32nd ACM/IEEE International Symposium on Microarchitecture, p. 62-71, November 1999.
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Other scholarly activity: grants, sabbaticals, software development, etc.:
- ``Quality of service management for enterprise-application computing utilities,'' National Science Foundation, $242,967, 2/04 - 12/06.
- ``Software Protection Techniques for Digital Rights Management,'' National Science Foundation, $100,000, 2/04 - 12/04.
- ``Self-Tuning Throughput Optimization Techniques for Wireless Mesh Networks,'' Computer Associates International, Inc., $124,125, 6/03 - 5/04.
- ``Vertical Handoff between WLAN and WWAN,'' Computer Associates International, Inc., $140,262, 6/03 - 5/04.
- ``Resource Virtualization for Cluster-Based Network Storage Service,'' National Science Foundation, $303,750, 9/02- 8/05.
- ``A Decoupled Architecture for Data-Intensive Compute Clusters,'' National Science Foundation, $128,000, 10/01 - 09/04.
- ``Implementation Techniques of Building Scalable Cluster-Based 3D Graphics Engines,'' National Science Foundation, $295,779, 1/00 - 12/04.
- ``Implementation Techniques for High-Performance Real-Time IP Routers,'' National Science Foundation, $297,000, 9/99 - 8/04.
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Scientific, professional, and honor societies of which you are a member:
IEEE and ACM |
Honors and awards:
1995 NSF Career Award |
Courses taught this and last academic year term-by-term:
Year/Term |
Course Number |
Course Title |
S05 |
CSE320 |
Computer Architecture |
F04 |
CSE649 |
Operating Systems |
F04 |
CSE591 |
Advanced Topics in CS |
S04 |
CSE320 |
Computer Architecture |
F03 |
CSE533 |
Fundamentals of Computer Networks |
F03 |
CSE684 |
Special Topics on Computer Security |
S03 |
CSE320 |
Computer Architecture |
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Academic advising:
- 14 Ph.D. students, 6 Master students, 1 Undergraduate student
- Assigned advisor for 18 undergraduate students during 2004/2005 academic year.
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Brief description of major research and scholarly activities:
My research activities involve building experimental computer systems that are faster, more reliable, and more secure. In particular, we focus on high-speed network devices, large-scale storage systems, and parallel graphics engines. |
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