CSE610 - Parallel Computer Architecture -
Spring 2005 v2 25Jan05
Lectures: 1441 Computer Science Mon, Wed
15.50-17:10 (3:50-5:10 pm)
Professor: Larry Wittie Office meetings : 1308 Comp Sci Bldg
Email: ldw@cs.sunysb.edu Office hours: MW 17:30-18:15pm (maybe
later also) (1308 CSB)
Phones:(Messages only)2-8456 (NetLab 1308)2-8750
Web: http://www.cs.sunysb.edu/~cse610
Required Text (price estimates from web
1/23/05): "In Search of Clusters" 2nd Edition, by Gregory Pfister, Prentice Hall, 1998 $45 ($25 used
at http://gettextbooks.com/search/?isbn=0-13-899709-8)
ISBN 0-13-899709-8 *****5 of 5
Recommended Text 1: "Computer
Architecture: A Quantitative Approach" THIRD Edition, by John Hennessy and David Patterson, Morgan-Kaufman, 2002 $90
($40 used at http://gettextbooks.com/search/?isbn=1-55860-596-7)
ISBN 1-55860-596-7***3.4 of 5
Recommended Text 2: "Parallel
Computer Architecture: A Hardware/Software Approach", by David Culler, J.P. Singh and Anoop Gupta,
Morgan-Kaufman, 1998 $90 ($40 used at http://gettextbooks.com/search/?isbn=1-55860-343-3)
ISBN 1-55860-343-3 ****4.3 of 5
Objectives: This course is a lecture survey of the major
objectives, constraints, and techniques for creating effective parallel
computing systems. This semester we will first read the Pfister text on the
power and limitations of grid machines (distributed computing). The material in chapters 6
(Multicomputers) and 8 (Networks) of the Hennessy and Patterson classic will be
supplemented by historical material from the Culler text, which is covers
mainly distributed shared memory parallel computing, culminating in the SGI
Origin 2000. Material on the Cray
MTA-2 (nee Tera MTA-1), the leading example of multithreaded architectural
support for shared memory supercomputing will be round out the coverage of
existing and historical parallel computing systems. Most of you already own Hennessy and Patterson. I have a few copies of Culler that can
be shared.
Explicitly parallel computing historically
has been the answer to the next increase in computing power for each generation
of technology, only to become an invisible part of future generations. The
1960s-70s had vector pipeline supercomputers. The 70s-80s, parallel machines of
many shapes to minimize switch delays for data sharing. The 80s-90s, shared
memory bus multiprocessors with scalar pipeline RISC mCPUs. The 90s-00s,
non-shared memory grid computers from racks of commodity (RISC and shared bus)
mCPUs connected by fast network switches. What is next? Muliprocessor chips.
Shared-memory grid machines spanning the globe. Invisible nanotech computing
grids in wall paper, with short-distance wireless links to global grid optical
fibers. Unobservable parallelism via quantum computing. What else?
Central themes will be how each architecture
seeks to execute certain classes of programs faster than a single processor,
the difficulty in accessing memory fast enough to keep the CPUs busy, the
de-emphasis of network topologies as propagation delays dominate switch delays
in both ultra-fast and Earth-grid computers, theoretical limits on parallel
program speedup, and memory sharing via caches for fewer than 500 CPUs and
multi-threading for massively parallel computers. Roughly 30% of the course
material will come from the Pfister essay, 30% of the course material will come
from the Hennessy and Patterson text, 20% of the course material will come from
the Culler text, mainly chapters 1, 8, and10; the rest from newer articles and
my own research.
Credits: 3
Lectures . . . . Assignments (most recent first, updated
1/25/05)
Projects (updated 0/0/00) . . . . Syllabus (updated 1/24/05)
NOTICES (most recent first)
====================================================
The class has moved to 1441 Computer Science. First homework is on the web in Lect01 and
Assignments. The grading weights
have been slightly altered in Syllabus.
====================================================
The class will be
moved to a room in Computer Science.
Check this website Monday 1/24/05 early afternoon. ======================================================================================
Whether registered or not, if you want to take
cse610 this semester:
name, email address,
dept, status at StonyBrook (example, CSE 2nd yr grad), registration
status for CSE610 (example, NOT Registered)
when and where you took
a computer architecture course (like our cse502 or cse320 or cse345) covering
instruction pipelines & memory caches, what course, your grade, max
possible grade
Any comments you wish
to make about your preparation and expectations for this course.
====================================================
=============