D. R. Smith, Office 1413,
email: drs, phone 2-8443, 941-3809
The project is to download one or more of the existing design examples from a new text [1] onto FPGA (field programmable gate array) chips on either the Altera UP1 or the Xilinx XS40 boards and then test. The source specification language is Verilog (similar syntax to 'C'), and other tools available are the Synopsys synthesizer and the FPGA fitter tools from Altera and Xilinx. The boards attach to the parallel port of a PC in the Experimental Systems Lab and the designs are downloaded using existing software (see also supplementary lab book [2] for Altera UP1 board).
Ideally students selecting this project would have taken or be taking the Digital Systems Synthesis course, CSE501. One incentive is that people conversant with this technology are even more highly sought after by industry than pure software engineers.