CSE 502 Computer Architecture (Spring 2011)

Recent Notices

Course Description

This is a graduate-level computer architecture course. Students who plan to take this course are expected to have the level of maturity in computer architecture provided in CSE320. If you do not have that background, you may have to work diligently in the first few weeks of this course to learn the material in Appendices A, B, and C of the text. This semester, after the initial review period, we will explore current trends in computer architecture, in particular, the head-long rush into parallel computing for modern commercial microprocessors, especially the development of energy-efficient multi-core processors, parallel-computer-networks-on-single-chips. Lectures will follow the lastest, 4th edition (2006) text rather closely, after a review of instruction pipelines (Appendix A) and memory hierarchies (Appendix C). A few relevant architecture papers may be made available on the website for students to read, critique, and discuss in class.

There will be a research project intended mainly for PhD students, an early preparedness assessment quiz, an in-class midterm exam, and a final exam, both exams open books/notes/lectures. In addition, there will be three or four very important homework sets, taken mainly from exercises in the text.

The final grade will be based on: 4% in-class Quiz, 8% (Optional) Research Project, 18% Homework, 20% Midterm, and 50% Final Exam. The workload is estimated to be 15 to 25 hours per week.

Administrative Matters

Special Needs

If you have a physical, psychological, medical or learning disability that may impact on your ability to carry out assigned course work, I would urge that you contact the staff in the Disabled Student Services office (DSS), Room 133 Humanities, 632-6748/TDD. DSS will review your concerns and determine, with you, what accommodations are necessary and appropriate. All information and documentation of disability is confidential.

Academic Dishonesty

You are encouraged to discuss the intellectual aspects of homework assignments with other class participants. However, each student is responsible for formulating solutions in his or her own words. Students who submit copied or suspiciously similar answers for examination or homework questions will receive a grade of zero for those questions and will have their final course score reduced substantially. The penalty will double each time copying occurs for another exam or assignment.
The surest way to fail computer architecture is blindly to copy from the web-based supposed "answers" for H+P text exercises. Most "answers" are terse; about 1/4th are wrong. If you do not work hard to solve the homework, you will not learn the technology well enough to pass the exams, especially the final exam.
In addition, the College of Engineering & Applied Sciences has formal procedures to handle cases of academic dishonesty. Each student must pursue his or her academic goals honestly and be personally accountable for all submitted work. Representing another person's work as your own is always wrong. Any suspected instance of academic dishonesty will be reported to the Academic Judiciary. For more comprehensive information on academic integrity, including categories of academic dishonesty, please refer to the academic judiciary website at http://www.stonybrook.edu/uaa/academicjudiciary/ .

All Notices

Reading and project handouts

This Semester (Spring '11) Lecture Slides

  • Lect01+2 Introduction Tu,Th 2/1,3/11 ppt / pdf
  • Lect03+4+5 Performance + PIPELINING Tu,Th,Tu 2/8,10,15/11 ppt / pdf updated 2/15/11.
  • Lect05+6 CACHEs, Virtual Memory, TLB Tu,Th 2/15,17/11 ppt / pdf updated 2/22/11.
  • Lect 07 finished TLB pages of Lect05+6 just before post-review in-class quiz, which will not be posted.
  • Lect08+9+10_Instruction_Level_Parallelism - Dependences, Loop Unrolling, Branch Prediction,
    Tomasulo Dynamic Scheduling HW Th 2/24, Tu,Th 3/1,3/11 (3/8 mainly quiz discussion) ppt / pdf updated 3/9/11
  • Lect11 ILP - Dynamic Scheduling + Speculation Th 3/10/11 ppt / pdf
  • Lect12+13 TLP - Threads and SMT - Simultaneous Multithreading Tu,Th 3/15-17/11 ppt / pdf
  • Lect14+15 Vector Processing Tu,Th 3/22-24/11 ppt / pdf
  • Lect 18 Return HW1 and explain answers Tu 4/5/11 (no answers posted)
  • Lect16+17+19+20 Symmetric Multiprocessing Tu,Th, Th,Tu 3/29,31-4/7,12/11 ppt / pdf
  • Lect 21 Midterm Review with Old 2002 MT plus Answers Th 4/14/11 pdf
  • Spring Break, no classes 4/19,21/11
  • Lect 22 Return HW2 and explain answers Tu 4/26/11 (no answers posted)
  • No lecture, MidTerm exam in class, Th 4/28/11 (not posted)
  • Lect 23 Directory. MP Synchronization Tu 5/3/11 ppt / pdf
  • Lect 24 Return MT and explain answers Th 5/5/11 (no answers posted)
    • Lect 25+26 Memory Hierarchy + Application Tuning Tu,Th 5/10,12/11 ppt / pdf

  • Past Semester (Spring '10) Lecture Slides

  • Lect01+2+3 Introduction M1/25-W1/27-M2/1/10 ppt / pdf
  • Lect03+4+5 Pipelining and Performance M2/1-W2/3-M2/8/10 ppt / pdf
  • Lect06+7 Memory Hierarchy cache + VM M2/15-W2/17/10 (2/10 snowed out) ppt / pdf
  • Lect08+9+10 Instruction Level Parallelism + Dynamic Scheduling W2/24-M3/1+M3/8/10 (2/22 was in-class quiz) ppt / pdf
  • Lect10+11 More Instruction Level Parallelism + Speculation M3/8-W3/10/10 ppt / pdf
  • Lect12+13 (Simultaneous) Multi-Threading M3/15-W3/17/10 ppt / pdf
  • Lect13+14+15 Vector Processing W3/17-M3/22-W3/24/10 ppt / pdf
  • M3/29+W3/31/10 are during spring break - no classes
  • Lect16+17+18 Symmetric MultiProcessing SMP M4/5-W4/7-M4/12/10 ppt / pdf
  • Lect19 Directory-based Cache Coherency and SMP Synchronization W4/14/10 ppt / pdf
  • Lect20 Midterm Review M4/19/10 doc / pdf
  • Lect21 Memory Hierarchy W4/28/10 ppt / pdf
  • Lect22 Disk Storage M5/3/10 ppt / pdf