Has hardware generation really been placed on a par with software?
In this talk we will first examine the characteristics and limitations of the present state of the art.
A high level synthesis style which we have been experimenting with at Stony Brook has its present incarnation originating from a writing style of the hardware design language "Verilog". Roughly speaking, the relationship of this style to Verilog is what C++ is to C.
The efficiency and economy of this style is demonstrated by a simulation of the well known pipelined DLX processor benchmark using only 430 lines of source. This is to be compared with about 3600 lines of source for the equivalent parts of an industrial simulation, and 500 lines of source for a toy processor in a recent text having only one quarter of the machine instructions. Furthermore this style is designed specifically to facilitate synthesis.
We discuss plans to use this style as the basis of laboratories in courses on architecture, VLSI, and FPGA in the departments of Electrical Engineering and Computer Science.