Specification for Hardware Synthesis

                                David R. Smith


The continuing advance of chip complexity has now passed the million
gate level. Such chips are tested by high performance simulators
running in a server ranch of around 1000 processors,
and this method is clearly reaching its limit.
Accordingly IC and CAD vendors are
desperately trying to develop methods based on verification by theorem
proving. However the industry is committed to specification languages
(Verilog and VHDL) which were not even designed for synthesis, and
present commercial verification tools are not practical at more than
about the 20,000 gate level. So the current buzzword is ``IP'', which
seeks to simplify the design problem with the extensive use of
previously designed and validated megamodules. An organization
is being set up to collect these, validate, and disseminate them.

A so far unconventional approach to the problem is to simplify the
original specification itself. We have been experimenting with a
number of implicit writing styles of Verilog which are between
3 and 9 times more economical than the explicit state machine method
commonly used for synthesis. Unlike the Synopsys behavioral compiler,
these methods permit (even encourage) the use of parameterized
submodules, but in an encapsulated manner. We envisage a
master style for rapid initial design exploration, translatable into
either the synchronous or asynchronous styles for synthesis.
The method also has the potential of making the source more
accessible to verification methods while yet staying within the
context of the industry standard hardware description languages.