The DASH is a scalable shared-memory MIMD machine that is being constructed at the Computer Systems Laboratory at Stanford University. Modified Silicon Graphics Power Series 4D/340 are being used as the building blocks for the clusters that form the DASH.
The system is being under the premise that it is possible to build a scalable high-performance machine with a single address space and coherent caches. The system is organized as a set of small clusters of processors. The memory is actually distributed among the clusters but a single address space is used for all the processors. A two-level cache system is used inside the clusters.
The scalability of the system comes from the two-level cache systems used inside the clusters and a directory-based cache coherence snooping system [33]. The system works as follows: every time a memory access is made, the hardware checks the first and second level caches, followed by the local main memory, if it still can not find the appropriate address, it fetches the address from non-local memory by using a look up table in the memory directory and the intercluster interface. This address will then be placed in the processor local cache and will be registered in the directories across the machines, so that if that address gets written to, the local cache line will be invalidated and the new value will need to be requested. The general assumption in the system is that memory reads are much more frequent than memory writes.
The current prototype has 8 clusters, each with four 33 MHz MIPS R3000/R3010 and 32 MB of memory for a total of 32 processors and 256 MB of main memory. Each cluster uses a two-level cache to improve performance.
The programming model for the DASH is exactly the same as for the Silicon Graphics Power Series. It extends UNIX with function calls to initiate processes on different processor queues, and it lets the user allocate local and shared memory. The conventional synchronization facilities are also supported.